| Signal type | Example pins (CH_A) | Count | |-------------|---------------------|-------| | DQ [0..63] | DQ0–DQ63 (spread across rows) | 64 | | DQS (strobe) | DQS0_t/c, DQS1_t/c | 8 pairs | | CA (CMD/ADDR) | A0–A17, BA0–BA1, BG0–BG1 | ~25 | | CLK | MEMCLK_A_t/c, MEMCLK_B_t/c | 2 pairs | | VDD_MEM | Multiple pins | ~20 | | VREF_CA, VREF_DQ | Reference voltage pins | 2 |
| Feature | CPU (e.g., 5900X) | APU (e.g., 5700G) | |---------|------------------|-------------------| | PCIe lanes usable | 20 (16+4) | 16 (8+4+4?) – actually 20 but with reduced GPU lanes | | Display outputs | Not present | DP, HDMI (eDP) pins | | VDD_GFX pins | NC (no connect) | Active power for GPU | | FCH interface | PCIe x4 | PCIe x4 (same) | | FCLK / UCLK | Unlocked | Same | am4 pin layout
Complete 1331-pin maps are maintained by the community at resources like "AM4 V1.6 Pinout" (IOShield). AM5 (LGA1718) replaced AM4 in 2022, moving to LGA to improve electrical reliability and support DDR5. However, AM4 remains widely used. Many AM4 pins (VDD_CORE, VSS, PCIe, DDR4) are electrically compatible with future CPUs only if voltage regulators support extended ranges (e.g., 1.8V I/O for DDR5 is not possible). | Signal type | Example pins (CH_A) |